The present invention relates to the technical field of frequency synthesizers, and in particular, it relates to a frequency synthesizer that can accurately compensate for ripple current.
The cellular telephone is a multi-frequency channel access system, and in order to shift the frequency being used for an open channel, a frequency synthesizer that can provide high-speed lock up is necessary.
The encoder 101 of FIG. 6 is a conventional device of this type of frequency synthesizer, and a PLL (phase-locked loop) circuit is used for the frequency divider system.
This frequency synthesizer 101 is provided within a semiconductor integrated circuit device that forms a transmit/receive circuit for a cellular telephone, and it has an oscillator 131, a frequency divider 132, a reference clock signal generator 133, a phase comparator 134, a charge pump circuit 135, a low-pass filter 136, and a control circuit 138. Within the oscillator 131, an external output signal (OUT) of a prescribed frequency is generated, and that external output signal (OUT) is output to the frequency divider 132 and to other circuits within the semiconductor integrated circuit device in which this frequency synthesizer 101 is provided.
The frequency divider 132 frequency divides the external output signal (OUT) that is input, generates a comparison signal, and outputs this comparison signal to the phase comparator 134. The said phase comparator 134 compares the phase of the comparison signal that is input from the frequency divider 132 and a reference clock signal that is input from the reference clock signal generator 133, and outputs a signal corresponding to the phase difference to the charge pump circuit 135. The charge pump circuit 135, based on the signal corresponding to the input phase difference, supplies an output signal, and that output signal is output to the oscillator 131 as a control signal via the low-pass filter 136.
The oscillator 131 changes the frequency of the external output signal (OUT) by means of this input control signal, and it is controlled so that the phase of the comparison signal matches the phase of the reference clock signal. As a result, the frequency of the external output signal (OUT) becomes the value of the frequency of the reference clock signal multiplied by the divisor value of the frequency divider 132.
The above-mentioned frequency divider 132 is controlled by means of the control circuit 138, and it is constructed so that the divisor value changes cyclically, for example, for the case where the frequency of the reference clock signal is 200 KHz, the value for seven cycles (35 xcexcsec) is 5000, and the value for one cycle (5 xcexcsec) is 5001, the average divisor value in which eight cycles are averaged becomes 5000.125 (=5000+xe2x85x9). Therefore, the frequency of the external output signal (OUT) is locked at the average divisor value multiplied by the reference clock signal, which is 1000025 KHz.
During eight cycles, if the divisor value for six cycles is 4000, and the divisor value for two cycles is 4001, the average divisor value is 4000.25, and the frequency of the external output signal (OUT) becomes 800.050 MHz.
In this way, if the average divisor value has values in columns to the right of the decimal point, narrow channel spacings of 25 KHz, 12.5 KHz, and the like, become possible for high frequencies such as 800 MHz and 1 GHz.
However, if the divisor value is cyclically changed as mentioned above, even after the external output signal (OUT) is locked at the desired frequency, the phase of the comparison signal and the phase of the reference clock signal are not completely synchronized, and a phase difference is generated. This phase difference is the cause of a cyclically changing ripple current within the signal that is output from the phase comparator 134.
The ripple current within the signal output from the phase comparator 134 causes the generation of transient components in the external output signal (OUT), which not only deteriorates reception characteristics of communications equipment such as cellular telephones, but it is also a source of interference during transmission, so ripple current is an enormous problem.
Thus, the compensating circuit 137 is provided in the above-mentioned frequency synthesizer 101. Within the compensating circuit 137, the amount of compensating current is set beforehand, and when a control signal from the control circuit 138 is input to the compensating circuit 137, a compensating current of the predetermined current amount is superimposed on the output signal of the charge pump circuit 135 at the timing at which that control signal is input, so that the ripple current can be removed, and so that an external output signal (OUT) without any transient components can be output.
The waveform of the ripple current and the compensating current contained in the output signal of the charge pump circuit 135 are respectively shown as symbols (a, b) in FIG. 7. The ripple current (a) changes cyclically as shown in FIG. 7, and the compensating current (b) also changes cyclically so as to follow the changes of the ripple current (a).
At this time, even if a compensating current (b) is generated that is equal to the size of the ripple current (a), if the generation time of the ripple current and the output time of the compensating current are not synchronized, as shown by symbol (c) in FIG. 7, the ripple component of the output signal of the charge pump circuit on which the compensating current is superimposed does not become zero, and there is the problem that the transient component cannot be removed accurately.
The present invention was created for the purpose of solving the unfavorable circumstances of the above-mentioned prior art, and its purpose is to offer technology which can accurately compensate for ripple current.
In order to solve the above-mentioned problems, the present invention has an oscillator that controls the frequency of an output signal according to a voltage control signal, a frequency divider that divides the above-mentioned output signal according to a frequency division value that changes cyclically and generates a comparison signal, a phase comparator that generates a phase difference signal by comparing the phase of the above-mentioned comparison signal and the phase of a reference clock signal, a delay circuit that generates and applies a delay to the above-mentioned phase difference signal, a charge pump circuit that generates a control signal corresponding to the phase difference signal that is output from the above-mentioned delay circuit, a low-pass filter that executes a prescribed wave filtering process on the above-mentioned control signal and outputs a voltage control signal, a compensating circuit that superimposes a compensating current on the above-mentioned control signal according to compensation voltage data, a detecting circuit that detects the output time of the above-mentioned control signal from the above-mentioned voltage control signal and the output time of the above-mentioned compensating current, and outputs a detection signal, wherein the above-mentioned delay circuit controls the supply of the above-mentioned compensating voltage data to the above-mentioned compensating circuit so that the output time of the above-mentioned control signal and the output time of the above-mentioned compensating current are synchronized.
One aspect of the present invention is based on the frequency synthesizer in which the detecting circuit, within one cycle at the time of the above-mentioned cyclic frequency divider, detects the time difference between the output time of the above-mentioned control signal and the output time of the above-mentioned compensating current by means of the above-mentioned voltage control signal that contains the above-mentioned superimposed compensating current and that is output at two times that bracket the times when the ripple current is at a maximum and a minimum.
The present invention constructed as described above has a detector circuit and a delay circuit, wherein the time difference between the output time for the output signal (control signal) of the charge pump circuit and the output time for the compensated current is detected by the detector circuit, and based on the detection results, one or both of the output time of the output signal and the output time of the compensating circuit are delayed by the delay circuit.
Therefore, for example, if the output signal is ahead of the compensating current, the timing for the output signal can be delayed by delaying the output time of the output signal by means of the delay circuit, and conversely, if the output signal lags behind the compensating current, since the timing for the compensating circuit can be delayed by delaying the output time of the compensating voltage data by means of the delay circuit, the time difference between the output time of the compensating current and the output time of the output signal can be corrected so that it is reduced.
In this way, the time difference between the output times is detected by the detecting circuit, the output time of the output signal for the compensating current is delayed, and after the output times of the output signal and the compensating current are corrected so that the time difference between the output times is small, in a condition in which the compensating current is output at the corrected output time, the time difference between the output times is detected again, the output time of the output signal for the compensating current is delayed, and the time difference between the output times is again corrected. If this type of operation is repeated a number of times, since the output times for the output signal and the compensating current can eventually be synchronized, it becomes possible to accurately remove the transient components.
In the present invention, output times where the compensating current brackets the times that the ripple current becomes a maximum and a minimum are detected twice by the detecting circuit.
After the ripple current has increased from minimum to maximum over one cycle of the frequency divider, it again decreases towards the minimum, and the compensating current, after decreasing from maximum to minimum, is output so as to again increase towards the maximum.
At this time, if the output time of the compensating current and the output time of the ripple current are synchronized, the output signal with the superimposed compensating current becomes 0, but if at first the output timing for the compensating current is delayed more than the output timing for the ripple current, since the absolute value of the compensating current is larger than the absolute value of the ripple current, the output signal with the superimposed compensating current becomes negative. After the ripple current becomes a maximum, since the absolute value of the ripple current becomes larger than the absolute value of the compensating current, the output signal with the superimposed compensating current becomes positive. Therefore, in this case, the output signal with the superimposed compensating current changes polarity from negative to positive at the times where the ripple current becomes a maximum.
Conversely, if the compensating current is ahead of the ripple current, the polarity of the output signal with the superimposed compensating current changes from positive to negative at the times where the ripple current becomes a maximum.
Therefore, if the polarity of the output signal with the superimposed compensating current is detected at two times that bracket the times when the ripple current becomes a maximum, it can be determined which of the output times is ahead of the other, and based on that detection result, one of either the compensating current or the ripple current is delayed by the delay circuit, and control can be performed so as to synchronize the output time of the compensating current at the output time of the ripple current.
Therefore, the output signal with the superimposed compensating current is detected, and the detection as to whether or not the ripple current has become 0 allows the detection of whether or not there is a time difference between the output time of the compensating current and the output time of the ripple current.